1. Field of the Invention
This invention relates to a semiconductor travelling wave amplifier and, more specifically, to a circuit for reducing gate loss in such circuits.
2. Description of the Prior Art
GaAs FET device technology and monolithic circuit implementation techniques have been combined successfully for the development of ultrabroadband distributed amplifiers. However, the output power of such amplifiers has been limited to less than 200 mW, even with a common drain line power combining techniques. Due to transmission line losses and gate line losses in particular, the total gate width of the amplifier cannot be increased without limit. This is due to the fact that per stage losses will ultimately equal or exceed the gain obtained by addition of further amplifier stages.
For a GaAs FET distributed amplifier, it can be shown that the gate and drain attenuation coefficients, .alpha..sub.g and .alpha..sub.d, are given by EQU .alpha..sub.g .congruent.(.omega.C.sub.g).sup.2 R.sub.g Z.sub.g /2 (1) EQU .alpha..sub.d .congruent.Z.sub.d /2R.sub.d ( 2)
In equations (1) and (2), Z.sub.g and Z.sub.d are the characteristic impedances of the gate and drain transmission lines. C.sub.g is the input (gate line) capacitance of an FET. R.sub.g and R.sub.d are input (gate line) and output resistances, respectively, of the FET. Due to the input and output resistances, significant losses are incurred as a result of dissipative loading. The attenuation of the gate line is particularly severe, due to the frequency dependent squared term. It is this attenuation that limits the maximum number of devices that can be implemented.